Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process

ABSTRACT

A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using a single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over the logic devices. Silicide spiking and bridging are prevented in the NVM cell, as silicide-blocking dielectric structure prevents silicide metal from coming in contact with the floating gate or adjacent sidewall spacers. The silicide-blocking dielectric layer may expose portions of the active regions of the NVM cell, away from the floating gate and adjacent sidewall spacers, thereby enabling silicide formation on these portions. Alternately, the silicide-blocking dielectric layer may cover the active regions of the NVM cell during silicide formation. In this case, silicide-blocking dielectric layer may be thinned or removed after silicide formation.

FIELD OF THE INVENTION

The present invention relates to non-volatile memory (NVM). Moreparticularly, this invention relates to non-volatile memory cellsfabricated using an ASIC or conventional logic process. In the presentapplication, a conventional logic process is defined as a semiconductorprocess that implements single-well or twin-well technology and uses asingle gate layer. This invention further relates to a method ofoperating a non-volatile memory to ensure maximum data retention time.

BACKGROUND OF INVENTION

Many modern integrated circuit applications demand the integration ofnon-volatile memory (NVM) and logic circuits on the same chip. However,traditional NVM cells are typically fabricated using a stacked gatestructure or a split gate structure. Therefore, a typical NVMfabrication process requires the deposition of more than one gate layer.In contrast, logic circuits are typically fabricated using asemiconductor integrated circuit manufacturing process that involves thedeposition of only one gate layer, which is deposited and patterned atthe same time for all devices on the chip. Such a single-gate process ishereinafter referred to as a conventional logic process. Because thesingle-gate layer used in a conventional logic process typicallyincludes polysilicon, this process is sometimes referred to as asingle-poly process.

The different requirements of traditional NVM circuits and logiccircuits makes it difficult to fabricate both of these circuits on thesame chip. The combination of an NVM circuit and a conventional logiccircuit therefore typically requires the use of a much more complicatedand expensive “merged non-volatile memory and logic” process, andresults in a high wafer price.

In order to resolve the NVM process integration challenge, various typesof planar CMOS NVM structures have been proposed. Such NVM structuresincorporate the single gate layer of the conventional logic process.More specifically, these NVM structures use patterned sections of thegate layer, which are left floating (i.e., have no associated gatecontact, and are isolated from the substrate by a gate dielectriclayer). These floating gates are selectively programmed or erased tostore predetermined charges. Each floating gate passes over a respectiveread device (i.e., read transistor), whereby the charge stored on eachfloating gate alters the conduction properties of the associated readdevice. These conduction properties are sensed during the readoperation. It is therefore essential that the charge stored on afloating gate manufactured in a conventional logic process is retainedfor as long as possible, thereby increasing the data retention time ofthe NVM system.

FIG. 1 is a cross-sectional view of a conventional NVM cell 100fabricated using a conventional logic process. NVM cell 100 isfabricated in substrate 101 and is isolated from other devices by fielddielectric region 114. In a conventional logic process, field dielectricregion 114 may be formed by filling a pre-etched substrate trench withdielectric, thereby forming a shallow-trench isolation (STI) region. NVMcell 100 includes source and drain contact diffusions 131 and 132,respectively, associated lightly doped source and drain extensiondiffusions 131A and 132A, gate dielectric layer 115, polysiliconfloating gate 116, metal silicide regions 141-143 and dielectricsidewall spacers 105-106. Gate dielectric layer 115 (which is typicallysilicon dioxide) isolates floating gate 116 (which is typicallyheavily-doped poly-silicon) from substrate 101. Silicide regions 141,142 and 143 are formed on the exposed upper surfaces of source contactregion 131, drain contact region 132 and floating gate 116,respectively. Silicide regions 141-143 are formed in the followingmanner. A refractory metal layer is initially deposited over the uppersurface of the NVM cell structure. Then, a reactive anneal is performed,which causes the metal layer to react with the underlying contactedsilicon regions to form silicide regions 141-143. Next, a metal strip isperformed, wherein the unreacted portions of the metal layer areremoved, but silicide regions 141, 142, and 143 are not removed. Becausesilicide regions 141-143 are self-aligned with the underlying siliconregions, these layers are sometimes referred to as salicide(self-aligned silicide) regions. Modern logic processes use metals suchas titanium (Ti), cobalt (Co), and nickel (Ni) to form silicide regions.The resulting silicides are attractive because of their ability tomaintain low resistivity in narrow diffusion and polysilicon gate lines,which are used in advanced processes.

However, the metal layer used to form silicide regions 141-143 mayundesirably react with silicon dioxide present in dielectric sidewallspacers 105-106 during the silicide formation process. This problem,which is commonly referred to as bridging, can result in the formationof conductive (silicide or metal) residue regions 144A-144B, which canshort floating gate 116 to the source and drain diffusion regions131-132, thereby creating a leakage path for charge to drain fromfloating gate 116.

The integrity of gate dielectric layer 115 is another concern associatedwith the formation of gate silicide region 143. Gate silicide region 143can spike through floating gate 116, as illustrated by silicide spike145 of FIG. 1. Silicide spike 145 degrades the performance of gatedielectric layer 115, and can potentially penetrate through gatedielectric layer 115 into silicon substrate 101, thereby causing aresistive short between floating gate 116 and substrate 101. In general,silicide spiking events are rare and result in minor local degradationof gate dielectric quality or a small gate dielectric leakage increasefor an entire chip that contains many millions of transistors. It is,however, critical to eliminate spiking events in gate dielectric layersthat are used in NVM cells, in order to preserve long floating gatecharge retention for all bits in the NVM memory. Silicide spiking eventsare expected to get worse as gate thickness scales in advanced processgenerations and as industry migrates to fully-silicided (FUSI) gates.

The problems introduced by NVM cell 100 are described in more detail inthe following references: [1] Ken-ichi et al., “A New Leakage Mechanismof Co Silicide and Optimized Process Conditions”, IEEE Transactions onElectron Devices, Vol. 4, No. 1, January 1999, pp. 117-124; and [2] S.Wolf, “Silicon Processing for the VLSI Era Volume 4—Deep-SubmicronProcess Technology”, Lattice Press, 2002, pp. 603-634.

It would therefore be desirable to have a NVM cell that can befabricated without modifying a conventional logic process (or requiringminimal modifications to a conventional logic process), and is notsusceptible to silicide spiking and silicide bridging.

SUMMARY

Accordingly, the present invention provides a non-volatile memory cell,which does not exhibit spiking or bridging, and is fabricated on thesame substrate as conventional logic devices, in accordance with aconventional logic process.

In one embodiment, the NVM cell includes an access transistor havingactive regions located in a semiconductor substrate, and a capacitorstructure having an active region located in the semiconductorsubstrate, wherein the access transistor and the capacitor structureshare a common polysilicon floating gate. Dielectric sidewall spacersare formed around the floating gate.

A silicide-blocking dielectric structure is formed over the floatinggate and the sidewall spacers prior to silicide formation. In accordancewith one embodiment, portions of the active regions of the accesstransistor and the capacitor, which are spaced away from the sidewallspacers, are exposed by the silicide-blocking dielectric structure.Silicide regions are then simultaneously formed on the exposed portionsof the active regions of the NVM cell and on the desired regions of thelogic devices.

In one embodiment, the silicide-blocking dielectric structure covers theentire floating gate. In another embodiment, the silicide-blockingdielectric structure can expose a section of the floating gate locatedover shallow trench isolation areas, such that silicide is formed overthis exposed section of the floating gate.

In accordance with another aspect of the invention, thesilicide-blocking dielectric structure may be formed such that thesilicide regions formed on the active regions of the NVM cell areseparated from the edges of these active regions. This advantageouslyminimizes the diffusion of metallic particles from these silicideregions through the field dielectric.

In another embodiment of the present invention, the silicide-blockingdielectric structure is formed entirely over the NVM cell, therebyblocking silicide formation on the active regions of the NVM cell. Aftersilicide formation has been performed for the logic devices, thesilicide-blocking dielectric structure is etched, thereby thinning orremoving this structure. A pre-metal dielectric layer is formed over theresulting structure, and a contact etch is performed to expose theactive regions of the NVM cell and the silicided regions of the logicdevices. Thinning (or removing) the silicide-blocking dielectricstructure ensures that the contact etch associated with a conventionallogic process will reliably expose the active regions of the NVM cell.

In another embodiment, the silicide-blocking dielectric structure is notthinned or removed. Instead, contact openings are formed in thepre-metal dielectric layer using a multi-etch procedure. In themulti-etch procedure, a partial etch is initially performed to createopenings in the pre-metal dielectric layer. These openings areselectively formed only at locations overlying the active regions of theNVM cells. A conventional contact etch is then performed. Thisconventional contact etch extends the openings formed during the partialetch, thereby exposing the active regions of the NVM cell. Theconventional contact etch also exposes the silicided regions of thelogic devices.

The present invention will be more fully understood in view of thefollowing description and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of a conventional non-volatile memorycell fabricated by a single-poly conventional logic process;

FIG. 2 is a top view of a non-volatile memory cell having a PMOS accesstransistor and an NMOS coupling capacitor in accordance with oneembodiment of the present invention;

FIGS. 3A and 3B are cross-sectional views along section lines A-A andB-B, respectively, of FIG. 2.

FIG. 4 is a cross-sectional view of an NVM cell, which does not includeany silicide regions, in accordance with an alternate embodiment of thepresent invention.

FIG. 5 is a top view of an NVM cell in accordance with yet anotherembodiment of the present invention, which includes a silicide regionformed on a neutral portion of the floating gate.

FIG. 6 is a top view of an NVM cell in accordance with anotherembodiment of the present invention, wherein silicide are formed awayfrom edges of the NVM cell active regions.

FIG. 7 is a cross-sectional view along section line C-C of FIG. 6.

FIG. 8 is a top view of an NVM cell in accordance with anotherembodiment of the present invention, which does not require theformation of silicide regions on the active regions of the NVM cell.

FIG. 9 is a cross-sectional view of the access transistor of the NVMcell of FIG. 8.

FIGS. 10A-10E are cross-sectional views illustrating a logic device andan access transistor of an NVM cell in accordance with one embodiment ofthe present invention, during various stages of fabrication.

FIG. 11 is a cross-sectional view of a logic device and an accesstransistor of an NVM cell, which illustrates a variation of theembodiment of FIGS. 10A-10E.

FIGS. 12A-12E are cross-sectional views illustrating a logic device andan access transistor of an NVM cell in accordance with anotherembodiment of the present invention, during various stages offabrication.

FIG. 13 is a cross-sectional view of a logic device and an accesstransistor of an NVM cell, which illustrates a variation of theembodiment of FIGS. 12A-12E.

DETAILED DESCRIPTION

FIG. 2 is a top layout view of a non-volatile memory cell 200 inaccordance with one embodiment of the present invention. FIG. 3A is across-sectional view of the non-volatile memory cell of FIG. 2 alongsection line A-A. FIG. 3B is a cross-sectional view of the non-volatilememory cell of FIG. 2 along section line B-B. Non-volatile memory cell200 can be operated in response to a positive Vdd supply voltage and aVss supply voltage of 0 Volts.

Note that the general layout of non-volatile memory cell 200 is similarto the layout of the NVM cell described in commonly owned U.S. Pat. No.6,512,691 (hereinafter, the '691 Patent). The portions of the '691Patent which describe the fabrication and operation of common elementsin the NVM cell 200 of the present invention and the NVM cell of the'691 Patent are hereby incorporated by reference. Although the presentinvention is described using a specific NVM cell 200, it is understoodthat the present invention is in no way limited to the particular layoutof non-volatile memory cell 200. As will become apparent in view of thefollowing disclosure, the present invention can be applied to any planarCMOS floating single-polysilicon NVM cell.

Non-volatile memory cell 200 is fabricated in a p-type monocrystallinesemiconductor substrate 201. In the described embodiment, substrate 201is silicon. Non-volatile memory cell 200 includes a PMOS accesstransistor 210. Access transistor 210 includes p-type source region 211and p-type drain region 212, which are formed in n-well region 202.Source region 211 includes lightly doped p-type source region 211A andp+ source contact region 211B. Drain region 212 includes lightly dopedp-type drain region 212A and p+ drain contact region 212B. An n-typechannel region 213 is located between source region 211 and drain region212. Source silicide region 251 is formed on an upper surface of sourcecontact region 211B. A virtual-ground contact (VGC) makes alow-resistance connection to source silicide region 251. Similarly,drain silicide region 252 is formed on an upper surface of drain contactregion 212B. A bit line contact (BLC) makes a low-resistance connectionto drain silicide region 252. Field dielectric 214 is located aroundsource region 211, drain region 212 and channel region 213 asillustrated. Field dielectric 214 is planarized, such that the uppersurface of field dielectric 214 and the upper surface of substrate 201are located in the same plane. A thin gate dielectric layer 215, whichis silicon oxide having a thickness between about 5 and 8 nm in thedescribed example, is located over channel region 213. Gate dielectriclayer 215 typically has the same thickness as the gate oxide layers usedin the input/output (I/O) transistors of a conventional logic process(not shown) fabricated in substrate 201. A conductively dopedpolycrystalline silicon floating gate 216 is located over thin gatedielectric layer 215. The logic transistors fabricated in substrate 201have control gate electrodes formed from the same polysilicon layer asfloating gate 216. Sidewall spacer 217, which is typically formed fromsilicon nitride or silicon oxide, is located at the edges of floatinggate 216.

Floating gate 216 and thin gate oxide 215 extend laterally beyond accesstransistor 210 over p-type substrate 201 and n-type coupling region 221.N-type coupling region 221 is coupled to n+ word line 222. N-typeregions 221-222, gate oxide 215 and floating gate 216 form an NMOScapacitor structure 220. NMOS capacitor structure 220 couples word line222 to floating gate 216. A capacitor silicide region 250 is formed onan upper surface of n+ diffusion word line 222. A word line contact(WLC) makes a low-resistance connection to capacitor silicide region252.

Silicide-blocking structure 218 is located over floating gate 216 andsidewall spacers 217. Silicide-blocking structure 218 is available in aconventional logic process, because a silicide-blocking layer isnormally used to prevent certain circuit elements, such as resistors,from becoming silicided. Silicide-blocking dielectric structure 218 isformed by blanket deposition of a silicide-blocking dielectric layerover the upper surface of the semiconductor structure after floatinggate 216, sidewall spacers 217, p-type source region 211, p-type drainregion 212, and n-type regions 221-222 have been formed, but before anysilicide has been formed. In the described embodiment, thesilicide-blocking dielectric layer is silicon dioxide, having athickness between 100 Angstroms and 500 Angstroms. The silicide-blockingdielectric layer is then patterned and etched away from the diffusionregions where contacts are to be formed, and from the regions of thesubstrate where logic devices (e.g., logic transistors) are to befabricated. Etching the silicide-blocking dielectric layer from theregions where logic devices are to be formed allows silicide to beformed on the desired regions (e.g., gates, drains and sources) of theselogic devices. After the etch is complete, silicide-blocking dielectricstructure 218 remains, covering polysilicon floating gate 216 andsidewall spacer 217.

A metal layer, such as titanium, cobalt, or nickel, (not shown) is thendeposited over the resulting structure. A reactive anneal is thenperformed. During the reactive anneal, the portions of the metal layerthat contact underlying silicon regions form metal silicide regions,including silicide regions 250, 251 and 252, which are formed over N+word line region 222, P+ source contact region 211B and P+ drain contactregion 212B. The unreacted portions of metal layer 245 are subsequentlyremoved, leaving the silicide regions. Contacts, including contacts WLC,VGC and BLC, are subsequently formed, thereby providing electricalcontacts to silicide regions, including silicide regions 250, 251 and252, respectively.

In the above-describe manner, NVM cell 200 can be fabricated using aconventional logic process, without any process modifications or specialimplants.

FIG. 4 is a cross-sectional view of an NVM cell 400 in accordance withan alternate embodiment of the present invention. The portion of NVMcell 400 illustrated by FIG. 4 corresponds with the portion of NVM cell200 illustrated by FIG. 3A. Because NVM cell 400 is similar to NVM cell200, similar elements in FIGS. 3A and 4 are labeled with similarreference numbers. As illustrated in FIG. 4, a silicide-blockingdielectric region 401 covers both floating gate 216 and NVM celldiffusion regions 211, 212 and 222 during silicide formation, such thatno silicide is formed on these diffusion regions 211, 212 and 222 orfloating gate 216. Openings through silicide-blocking dielectric region401 are subsequently formed, thereby allowing word line contact WLC tocontact capacitor diffusion region 222 (shown), and allowing contactsVGC and BLC to contact their respective diffusion regions 211 and 212(not shown). In this embodiment, it is essential that the contact etchetches completely through silicide-blocking dielectric region 401, SO asto guarantee that the NVM cell contacts touch their respective diffusionregions. Layout methods for ensuring that NVM cell contacts touch theirrespective diffusion regions are described in connection with FIGS. 3, 5and 6. Process methods for ensuring that the etch extends completelythrough silicide-blocking dielectric region 401 are described in moredetail below, in connection with FIGS. 9, 10A-10E, 11, 12A-12E and 13.

FIG. 5 is a top view of an NVM cell 500 in accordance with anotherembodiment of the present invention. Because NVM cell 500 issubstantially identical to NVM cell 200, similar elements in FIGS. 2 and5 are labeled with similar reference numbers. The main differencebetween NVM cells 200 and 500 is that the silicide-blocking dielectricregion 218 of NVM cell 200 is divided into two separatesilicide-blocking dielectric regions 218A and 218B in NVM cell 500. Thespace between separate silicide-blocking dielectric regions 218A and218B exposes a portion of gate electrode 216. Thus, during thesilicidation step, a silicide region 501 is formed on this exposedportion of gate electrode 216. Silicide region 501 advantageouslyincreases the conductivity of the central region of floating gate 216.

Note that the portion of floating gate 216 associated with accesstransistor 210 (and covered by silicide-blocking region 218A) is exposedduring the P− and P+ implant steps. Similarly, the portion of floatingelectrode 216 associated with capacitor structure 220 (and covered bysilicide-blocking region 218B) is exposed during the N- and N+ implantsteps. Misalignment of the N-type and P-type implant masks, along withdopant cancellation, creates a neutral region in the area of the P-Njunction of the floating gate 216 (i.e., the region where silicideregion 501 is formed). This neutral region has a lower conductivity thanthe remainder of floating gate 216. Consequently, the location ofsilicide region 501 is selected to correspond with this neutral region,thereby providing a conductive path between the heavily doped P+ and N+regions of floating gate 216.

It is important to note that silicide region 501 is located over fielddielectric region 214, and not over an active region of the NVM cell500. Thus, even if silicide region 501 spikes through floating gate 216,or bridges over sidewall spacer 217, there is no conductive path throughwhich the charge on the floating gate 216 can leak away. That is,spiking or bridging will only allow silicide region 501 to contact theunderlying field dielectric region 214. However, while thesilicide-blocking regions may expose portions of the floating gate thatextend over field dielectric region, those silicide-blocking regions atthe same time cover the portions of the floating gate that extend overactive regions of the NVM cell.

FIG. 6 is a top view of an NVM cell 600 in accordance with anotherembodiment of the present invention. Because NVM cell 600 issubstantially identical to NVM cell 200, similar elements in FIGS. 2 and6 are labeled with similar reference numbers. The main differencebetween NVM cells 200 and 600 is that the NVM cell 600 uses asilicide-blocking dielectric region 601 that is laid out differentlythan the silicide-blocking dielectric region 218 of NVM cell 200.Silicide-blocking dielectric region 601 covers the entire NVM cell 600,except for the three locations where openings 601A, 601B and 601C areformed through the silicide-blocking dielectric region 601. Openings601A, 601B and 601C expose the locations where silicide regions are tobe formed in capacitor region 222, source region 211 and drain region212, respectively. Silicide regions 650, 651 and 652 are formed throughopenings 601A, 601B and 601C, respectively. In accordance with thepresent embodiment, silicide regions 651-653 of NVM cell 600 are not indirect contact with the field dielectric region 214. That is, silicideregions 650, 651 and 652 are separated from field dielectric region 214(and thereby the edges of the associated active regions) by thinsections of capacitor region 222, source region 211 and drain region212, respectively. This structure advantageously minimizes themicro-diffusion of metallic particles from silicide regions 650-652through field dielectric region 214. Such micro-diffusion may be aconcern if the field dielectric region 214 is fabricated using an STIprocess, wherein the field oxide is not as dense as thermally-grownoxide, and is therefore susceptible to micro-diffusion.

FIG. 7 is a cross-sectional view along section line C-C of FIG. 6, whichillustrates the above-described micro-diffusion issue in more detail. Asshown in FIG. 7, metallic particles of silicide regions 651 and 652could diffuse relatively easily along paths 701 and 702, respectively,but for the portions of source and drain regions 211 and 212, whichseparate silicide regions 651 and 652 from field dielectric region 214.Because metallic particles in silicide regions 651 and 652 do notdiffuse easily through these portions of source and drain regions 211and 212, there is no significant diffusion of metallic particles alongpaths 701 and 702. Note that if metallic particles were to diffuse fromsilicide regions 651 and 652 along paths 701 and 702, a resistiveconduction path could be provided between floating gate 216 and silicideregions 651 and 652 along these paths 701-702, even though floating gate216 and sidewall spacer 217 are protected by silicide-blockingdielectric region 601.

Note that forming openings 601A-601C in silicide-blocking region 601 mayincrease the NVM cell size, because openings 601A-601C may be relativelylarge, if formed using a conventional logic process. In a conventionallogic process, the silicide-blocking structures are typically used toprevent the formation of silicide on large resistor structures.Consequently, the patterning of the silicide-blocking structures in aconventional logic process are typically only required to conform withdesign rules which are much less precise (and therefore larger) than theminimum design rules. If openings 601A-601C are patterned using thelarger design rules, these openings will be relatively large, increasingthe NVM cell size.

FIG. 8 is a top view of an NVM cell 800, which is similar to NVM cell600, but does not require forming openings 601A-601C or silicide regions650-652. Because NVM cell 800 is similar to NVM cell 600, similarelements are labeled with similar reference numbers in FIGS. 6 and 8.NVN cell 800 includes a silicide-blocking dielectric structure 801,which covers the entire NVM cell 800. That is, silicide-blockingdielectric structure 801 does not include the openings 601A-601C foundin silicide-blocking dielectric structure 601.

FIG. 9 is a cross-sectional view of the access transistor 210 of NVMcell 800 and a logic transistor 910, which are fabricated on the samesubstrate 201. The illustrated portion of logic transistor 910 includesp-type source region 911, gate dielectric layer 915, polysilicon controlgate 916 and dielectric sidewall spacer 917. P-type source region 911includes p-type source extension region 911A and P+ source contactregion 911B. Silicide-blocking dielectric structure 801 extends overaccess transistor 210 and a portion of field dielectric region 214, butdoes not extend over logic transistor 910. A conventional contact etchwill not reliably etch completely through silicide-blocking dielectricstructure 801.

FIG. 10A is a cross-sectional view of access transistor 210 and logictransistor 910, after a metal layer 1001 (e.g., titanium, cobalt,nickel) has been deposited over the structure of FIG. 9. After metallayer 1001 has been deposited, an anneal is performed, such thatsilicide is formed in the regions 1011-1012 where metal layer 1001contacts underlying silicon. The unreacted portions of metal layer 1001are then removed, leaving silicide regions 1021 and 1022 as illustratedin FIG. 10B.

As illustrated in FIG. 10C, an etch is then performed to thinsilicide-blocking dielectric structure 801, thereby creating thinnedsilicide-blocking dielectric structure 801A. Alternately,silicide-blocking dielectric structure 801 can be completely removed bythis etch. Note that exposed portions of field dielectric region 214 maybe etched during this step, as illustrated by etched region 1030.

As illustrated in FIG. 10D, a pre-metal dielectric layer 1050 is formedover the structure of FIG. 10C. A contact etch is then performed inaccordance with the conventional logic process, thereby forming openings1051-1054 in pre-metal dielectric layer 1050. Openings 1051-5054 exposesilicide region 1022 on control gate 916, silicide region 1021 on sourcecontact region 911, drain contact region 212 and source contact region211, respectively. The reduced thickness of thinned silicide-blockingdielectric structure 801A ensures that the conventional contact etchreliably exposes non-silicided diffusion regions 211 and 212. Note thatpre-metal dielectric layer 1050 fills etched region 1030.

As illustrated in FIG. 10E, electrically conductive contacts 1061, 1062,BLC and VGC are formed in openings 1051-1054, respectively, therebymaking contact to silicide region 1022, silicide region 1021, P+ draincontact region 212 and P+ source contact region, respectively.

FIG. 11 is a cross-sectional view of access transistor 210 and logictransistor 910, which illustrates a variation of the embodiment of FIGS.10A-10E. In FIG. 11, a photoresist mask 1100 is formed over thestructure illustrated in FIG. 10B. Photoresist mask 1100 requires anadditional masking step not usually found in a conventional logicprocess. The silicide regions 1021-1022 (and the other silicided regionsin the logic devices) are covered by photoresist mask 1100. Other logicdevices (e.g., resistors), which are covered by silicide-blockingdielectric structures (not shown), may also be covered by photoresistmask 1100. An opening in photoresist mask 1100 exposes the NVM cells,including silicide-blocking dielectric structure 801. Silicide-blockingdielectric structure 801 is etched through the openings in photoresistmask 1100, thereby thinning (or removing) this structure in the mannerdescribed above in connection with FIG. 10C. Photoresist mask 1100 isthen stripped, and processing continues as described above in connectionwith FIGS. 10C-10E. Note that etched region 1030 does not exist in theembodiment illustrated by FIG. 11.

FIG. 12A is a cross-sectional view of access transistor 210 and logictransistor 910 in accordance with yet another embodiment of the presentinvention. In this embodiment, pre-metal dielectric structure 1250 isformed over the structure illustrated in FIG. 10B. That is, pre-metaldielectric structure 1250 is formed without thinning (or removing)silicide-blocking dielectric structure 801.

Photoresist layer 1251 is formed over pre-metal dielectric structure1250, as illustrated in FIG. 12B. Photoresist 1251 is exposed anddeveloped to form openings 1211 and 1212, which define the locationswhere contacts of NVM cells are to be formed. A partial etch isperformed through openings 1211 and 1212, thereby forming etched regions1221 and 1222 in the upper surface of pre-metal dielectric structure1250. This partial etch represents a step in addition to a conventionallogic process.

As illustrated in FIG. 12C, photoresist layer 1251 is exposed anddeveloped a second time, thereby forming openings 1213 and 1214, whichdefine the locations where contacts to silicide regions 1021 and 1022are to be formed. The second exposure/develop step represents anadditional step in a convention logic process.

As illustrated in FIG. 12D, a conventional contact etch is performedthrough openings 1211-1214 of photoresist mask 1251, thereby formingcontact openings 1231-1234, which expose p-type source 211, p-type drain212, silicide region 1021 and silicide region 1022, respectively.Partially etched regions 1221-1222 ensure that this contact etchreliably extends completely through silicide-blocking dielectric region801. Photoresist mask 1251 is then stripped, and contacts 1241-1244 areformed in contact openings 1231-1234, respectively, as illustrated inFIG. 12E.

FIG. 13 is a cross-sectional view of access transistor 210 and logictransistor 910, which illustrates a variation of the embodiment of FIGS.12A-12E. As illustrated in FIG. 13, the photoresist mask 1251 of FIG.12B is stripped after NVM contact openings 1221 and 1222 have beenformed by the partial etch step. A second photoresist mask 1300 is thenformed over the resulting structure, as illustrated in FIG. 13.Photoresist mask 1300 includes openings 1301-1304, which are located inthe same locations as openings 1211-1214, respectively, in thephotoresist mask 1251 of FIG. 12C. Processing continues in the mannerdescribed above in connection with FIGS. 12C-12E.

Although the present invention has been described in connection withseveral embodiments, it is understood that this invention is not limitedto the embodiments disclosed, but is capable of various modificationswhich would be apparent to one of ordinary skill in the art. Thus,although the present invention has been described in conjunction with aparticular planar NVM cell using a single layer of gate electrodematerial, it is understood that the general nature of the presentinvention does not preclude application to any planar NVM cell. In otherembodiments, openings in the pre-metal dielectric structure can beetched through hard-mask film openings serving as etch windows, whilehard-mask film openings themselves are defined by patterned photoresist.Thus, the invention is limited only by the following claims.

1. A non-volatile memory system including one or more non-volatilememory cells, each comprising: a plurality of active semiconductorregions; a floating gate electrode extending over portions of the activesemiconductor regions, the floating gate electrode connecting variouselements of the non-volatile memory cell; and a patternedsilicide-blocking layer located over the floating gate electrode, thepatterned silicide-blocking layer fully covering and preventing silicideformation on portions of the floating gate electrode located over theactive semiconductor regions.
 2. The non-volatile memory system of claim1, wherein the patterned silicide-blocking layer exposes portions of theactive semiconductor regions, wherein silicide is formed on the exposedportions of the active semiconductor regions.
 3. The non-volatile memorysystem of claim 2, wherein the patterned silicide-blocking layer extendsover active semiconductor regions of the non-volatile memory cells. 4.The non-volatile memory system of claim 1, wherein the patternedsilicide blocking layer extends over the active semiconductor regions,thereby preventing silicide formation on the active semiconductorregions.
 5. The non-volatile memory system of claim 1, wherein thefloating gate electrode is doped with p-type and n-type impurities. 6.The non-volatile memory system of claim 5, further comprising an activeisolation region, wherein the floating gate electrode includes a p-ninterface located over the active isolation region.
 7. The non-volatilememory system of claim 6, wherein the patterned silicide-blocking layerexposes the p-n interface of the floating gate electrode, whereinsilicide is formed on the p-n interface of the floating gate electrode.8. The non-volatile memory system of claim 1, wherein each of the one ormore non-volatile memory cells further comprises a dielectric sidewallspacer located immediately adjacent to the floating gate electrode,wherein the patterned silicide-blocking layer extends over thedielectric sidewall spacer.
 9. The non-volatile memory system of claim8, wherein the patterned silicide-blocking layer entirely covers thefloating gate electrode and the dielectric sidewall spacer.
 10. Thenon-volatile memory system of claim 1, wherein the patternedsilicide-blocking layer comprises a dielectric material.
 11. Thenon-volatile memory system of claim 1, wherein silicide regions arelocated on the active semiconductor regions, the silicide regions beinglocated entirely within, and separated from, edges of the activesemiconductor regions.
 12. The non-volatile memory system of claim 1,wherein the patterned silicide-blocking layer has a thickness that issubstantially less than an initially deposited thickness of materialused to create the patterned silicide-blocking layer.
 13. Thenon-volatile memory system of claim 1, wherein each of the one or morenon-volatile memory cells includes an access transistor and a capacitorstructure, which are connected by the floating gate electrode.
 14. Amethod of fabricating anon-volatile memory system including one or morenon-volatile memory cells, each comprising: forming a plurality ofactive regions in a semiconductor substrate; forming a floating gateelectrode over portions of the active semiconductor regions, thefloating gate electrode connecting various elements of the non-volatilememory cell; and forming a patterned silicide-blocking layer over thefloating gate electrode, whereby the patterned silicide-blocking layerfully covers and prevents silicide formation on portions of the floatinggate electrode located over the active semiconductor regions.
 15. Themethod of claim 14, wherein the step of forming the patternedsilicide-blocking layer comprises exposing portions of the activesemiconductor regions, the method further comprising forming silicide onthe exposed portions of the active semiconductor regions.
 16. The methodof claim 15, wherein the step of forming the patterned silicide-blockinglayer results in the patterned silicide-blocking layer extending overactive semiconductor regions of adjacent non-volatile memory cells. 17.The method of claim 14, further comprising using the patternedsilicide-blocking layer to prevent silicide formation on the activesemiconductor regions.
 18. The method of claim 14, further comprising:doping a first region of the floating gate electrode with p-typeimpurities; and doping a second region of the floating gate electrodewith n-type impurities, wherein a p-n interface is formed in thefloating gate electrode.
 19. The method of claim 18, further comprising:forming an active region isolation region in the semiconductorsubstrate; and forming the p-n interface over the active isolationregion.
 20. The method of claim 19, wherein the step of forming thepatterned silicide-blocking layer comprises exposing the p-n interfaceof the floating gate electrode, the method further comprising formingsilicide on the exposed p-n interface of the floating gate electrode.21. The method of claim 14, further comprising: forming a dielectricsidewall spacer adjacent to the floating gate electrode; and forming thepatterned silicide-blocking layer such that the patternedsilicide-blocking layer covers the dielectric sidewall spacer.
 22. Themethod of claim 14, further comprising forming silicide regions on theactive semiconductor regions, the silicide regions being locatedentirely within, and separated from, edges of the active semiconductorregions.
 23. The method of claim 14, further comprising: formingsilicide, wherein the patterned silicide-blocking layer covers theentire non-volatile memory cell, preventing silicide formation thereon;performing an etch which reduces the thickness of the patternedsilicide-blocking layer; and then performing a contact etch whichextends through the patterned silicide-blocking layer.
 24. The method ofclaim 23, wherein the etch is selective to silicon, wherein the etch isperformed until the silicide blocking layer is completely removed. 25.The method of claim 23, wherein the step of performing the etch furthercomprising: forming a mask which exposes the non-volatile memory cellsystem and protects other regions of the semiconductor substrate; andthen performing the etch of the silicide blocking layer through themask.
 26. The method of claim 14, further comprising: forming silicide,wherein the patterned silicide-blocking layer prevents silicideformation on portions of the floating gate electrode located over theactive semiconductor regions; then forming a pre-metal dielectric overthe silicide and the patterned silicide-blocking layer; forming a firstmask over the pre-metal dielectric, wherein the first mask includesopenings where contacts are to be formed through the patternedsilicide-blocking layer; performing a partial etch of the pre-metaldielectric through the openings in the first mask; forming a second maskover the pre-metal dielectric, wherein the second mask includes openingswhere all contacts are to be formed; and then performing a contact etchthorugh the openings of the second mask, wherein the contact etchextends through the patterned silicide-blocking layer.
 27. The method ofclaim 26, wherein the step of forming the second mask comprisesdepositing a hard-mask film.
 28. The method of claim 26, furthercomprising: forming the first mask by forming a first set of openingsthrough a photoresist layer; and forming the second mask by subsequentlyforming a second set of openings through the photoresist layer.
 29. Themethod of claim 26, further comprising: forming the first mask byforming a first set of openings through a first photoresist layer; andforming the second mask by forming a second set of openings through asecond photoresist layer.